The present invention relates to a double diffusion insulated gate field effect transistor (DMOS) and a semiconductor integrated circuit device including the DMOS.
FIG. 2 is a cross-sectional view showing processes in a conventional manufacturing method for manufacturing a double diffusion insulated gate field effect transistor (hereinafter referred to as xe2x80x9cDMOSxe2x80x9d) used in a semiconductor integrated circuit device. As an example, an n-channel lateral double diffusion insulated gate field effect transistor (hereinafter referred to as xe2x80x9cLDMOSxe2x80x9d) will be described. First, after a gate insulating film 3 for forming an LDMOS and a field insulating film 2 for element separation are formed on an n-type semiconductor substrate 1 (FIG. 2(a)), impurities of the same conductivity as that of the above-described semiconductor substrate, for example, arsenic is implanted (channel doped) in a region of the gate insulating film 3 where the LDMOS is formed in order to adjust a threshold voltage of the LDMOS (FIG. 2(b). An angle at which the impurities are implanted is generally inclined by about 7xc2x0 from a direction perpendicular to the substrate in order to prevent a channeling phenomenon.
Then, a polycrystal silicon film is deposited through LPCVD. In order that the polycrystal silicon is used as a gate electrode of the LDMOS, the polycrystal silicon film is formed in the thickness of 2000 to 4000 xc3x85. Subsequently, in order that the polycrystal silicon is used as a low-resistant electrode, impurities are implanted in the polycrystal silicon film with a high concentration through thermal diffusion at 890xc2x0 C. The impurities are made of phosphorus, the concentration of impurity is 1020 atoms/cm3 or more, and the resistant value of the polycrystal silicon film per unit length and unit width, that is, a sheet resistance is a low resistance such as 100 xcexa9/xe2x96xa1 or less. Then, the polycrystal silicon is patterned in the form of a gate electrode 4 (FIG. 2(c)).
Thereafter, the gate insulating film 3 on the semiconductor substrate surface is etched by an etchant such as HF. In this situation, the field insulating film 2 is etched as thick as that of the gate insulating film so as to be reduced in thickness, and the gate insulating film is etched in a region where the gate insulating film is formed but no gate electrode is formed to expose the semiconductor substrate 1. Then, a thermal oxide film 10 is formed through thermal oxidation in thickness of 100 to 300 xc3x85 in the region where the semiconductor substrate 1 is exposed. Subsequently, in order to form a body region 7 of the LDMOS, impurities of the conductivity opposite to that of the semiconductor substrate, for example, boron is implanted into a region that will form a source of the LDMOS in a self-alignment manner using a photo-resist 9 and the gate electrode 4 as a mask (FIG. 2(d)).
Then, in order to make the impurities in the body region diffuse, a heat treatment is conducted (FIG. 2(e)). The heat treatment is conducted at a high temperature of 1000xc2x0 C. or higher in order to make the impurities for the body diffuse up to desired distances in a depthwise direction and a lateral direction of the semiconductor substrate. In this situation, the channel doping impurities which have been implanted in a previous step are diffused at the same time.
Subsequently, impurities, for example, arsenic is implanted in source/drain regions 5 and 6 of the LDMOS through ion implantation (FIG. 2(f)). The concentration of impurities is high to the degree of 1020 atoms/cm3 or more. Thereafter, although not shown, an intermediate insulating film is formed on the semiconductor substrate. Contact holes are formed on the substrate where the source and the drain have been formed. Then, metal wirings are formed for electrically connecting the respective parts of the circuit. The metal wirings are generally formed of aluminum wirings.
However, the conventional method suffers from problems stated below.
Because the heat treatment is conducted for diffusion in the body region after the channel doping process, the heat treatment causes the concentration of the impurities with which the channel doping has been made on the semiconductor substrate surface to be lowered. This makes it impossible to lower the threshold voltage of the DMOS. Also, when the dope amount of impurities for channel doping increases in order to lower the threshold voltage, the channel doping impurities are caused to diffuse up to the deep portion of the substrate. Then, the impurities in the body region whose conductivity is opposite to that of the channel doping impurities are negated by the channel doping impurities in the deep portion of the substrate, resulting in such phenomenons that the effective concentration of impurities in the body is lowered, and the channel length is shortened. Also, the impurity concentration in a region except for the body region under the gate electrode becomes high. As a result, a source/drain withstand voltage is deteriorated due to punch-through.
For that reason, the impurity dose of the channel doping must be reduced in order to prevent the withstand voltage from being deteriorated, and therefore the threshold voltage cannot be set to be low.
Under the above circumstances, in order to solve the above problems with the conventional device, an object of the present invention is to prevent the deterioration of the source/drain withstand voltage due to the punch-through which is caused by the channel doping process, and to realize a low threshold voltage.
In order to solve the above problems, a method of manufacturing a semiconductor integrated circuit device according the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of a first conductive type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of a second conductive type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting the impurities of the first conductive type into the body region of the second conductive type with an inclination exceeding 7xc2x0, in a direction of from the drain region toward the source region on the same element, with respect to a direction perpendicular to the semiconductor substrate; a step of implanting the impurities of the first conductive type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.
Also, a method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of a first conductive type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of a second conductive type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting the impurities of the first conductive type into the body region of the second conductive type with an inclination exceeding 7xc2x0 with respect to a direction perpendicular to the semiconductor substrate while rotating the semiconductor substrate in a planar direction; a step of implanting the impurities of the first conductive type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of an n-type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of a p-type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting phosphorus into the body region of the p-type at an angle of from 45xc2x0 to 60xc2x0 with respect to a direction perpendicular to the semiconductor substrate with an implantation energy of from 70 keV to 180 keV while rotating the semiconductor substrate in a planar direction; a step of implanting the impurities of the n-type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of an n-type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of a p-type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting arsenic into the body region of the p-type at an angle of from 40xc2x0 to 60xc2x0 with respect to a direction perpendicular to the semiconductor substrate with an implantation energy of from 120 keV to 180 keV while rotating the semiconductor substrate in a planar direction; a step of implanting the impurities of the n-type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of a p-type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of an n-type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting boron into the body region of the n-type at an angle of from 45xc2x0 to 60xc2x0 with respect to a direction perpendicular to the semiconductor substrate with an implantation energy of from 40 keV to 180 keV while rotating the semiconductor substrate in a planar direction; a step of implanting the impurities of the p-type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is characterized by comprising: a step of forming a gate insulating film on a semiconductor substrate of a p-type; a step of forming a polycrystal silicon film of 2000 to 4000 xc3x85 on the gate insulating film; a step of implanting impurities 1020 atoms/cm3 or more in concentration into the polycrystal silicon film; a step of etching the polycrystal silicon film to form a gate electrode; a step of etching the gate insulating film where no gate electrode has been formed; a step of forming a thermal oxide film of 100 to 300 xc3x85 on the semiconductor substrate where the gate insulating film has been etched; a step of implanting impurities of an n-type which will form a body region into a source region of a double diffusion insulated gate field effect transistor in the semiconductor substrate on which the thermal oxide film has been formed; a step of conducting a heat treatment on the semiconductor substrate at a temperature of 1000xc2x0 C. or higher; a step of implanting BF2 into the body region of the n-type at an angle of from 40xc2x0 to 60xc2x0 with respect to a direction perpendicular to the semiconductor substrate with an implantation energy of from 100 keV to 180 keV while rotating the semiconductor substrate in a planar direction; a step of implanting the impurities of the p-type into the source/drain regions of the double diffusion insulated gate field effect transistor; a step of forming an intermediate insulating film on the thermal oxide film and the polycrystal silicon; a step of forming contact holes in the intermediate insulating film; and a step of providing metal wirings in the contact holes.